1. Field of the Invention
The information disclosed herein relates generally to a recessed gate transistor, and more particularly to a recessed gate transistor with buried fins.
2. Description of the Prior Art
Techniques for the manufacture and production of semiconductor devices are being developed worldwide, based on requirements of semiconductor users and semiconductor manufacturers. Thus, designing to integrate more semiconductor devices in a semiconductor chip of limited size reduces an interval between gates, causing a short channel effect, a leakage current, and other difficulties.
In order to solve these shortcomings, it is well known in the art of a recessed gate transistor is provided. The recessed gate transistor has a gate insulation layer formed on both side walls and bottom face of a recess formed in a substrate, and a conductive layer, such as polysilicon, fills in the recess.
However, according to the related art, a leakage is generated by a concentration of an electric field because only a thin oxide layer is interposed between the active region and the gate. This, in effect, extends the contact region between the active region and the gate. This causes an increased load capacity and gate induced drain leakage (GIDL). These problems may deteriorate the operating performance of the devices.